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INTEGRATED CIRCUITS
DATA SHEET
TDA4662 Baseband delay line
Product specification Supersedes data of 1995 Oct 30 File under Integrated Circuits, IC02 1996 Nov 14
Philips Semiconductors
Product specification
Baseband delay line
FEATURES * Two comb filters, using the switched-capacitor technique, for one line delay time (64 s) * For PAL and NTSC * Adjustment-free application * Handles negative or positive colour-difference input signals * Clamping of AC-coupled input signals [(R-Y) and (B-Y)] * VCO without external components * 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 s line) * Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal * Addition of delayed and non-delayed output signals * Output buffer amplifiers * Comb filtering functions for NTSC colour-difference signals to suppress cross-colour. QUICK REFERENCE DATA SYMBOL VP1 VP2 IP(tot) Vi(p-p) Gv PARAMETER analog supply voltage (pin 9) digital supply voltage (pin 1) total supply current MIN. 4.5 4.5 - 5 5 5.5 525 665 5.8 5.8 TYP. 6 6 GENERAL DESCRIPTION
TDA4662
The TDA4662 is an integrated baseband delay line circuit with one line delay. It is suitable for PAL and NTSC decoders with colour-difference signal outputs (R-Y) and (B-Y).
MAX. V V
UNIT
7.0 - - 6.3 6.3
mA mV mV dB dB
(R-Y) input signal PAL/NTSC (peak-to-peak value; pin 16) - (B-Y) input signal PAL/NTSC (peak-to-peak value; pin 14) - voltage gain VO/VI of colour-difference output signals V11/V16 for PAL and NTSC V12/V14 for PAL and NTSC 5.3 5.3
ORDERING INFORMATION TYPE NUMBER TDA4662 TDA4662T PACKAGE NAME DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm VERSION SOT38-4 SOT109-1
1996 Nov 14
2
1996 Nov 14
BLOCK DIAGRAM
Philips Semiconductors
Baseband delay line
handbook, full pagewidth
(R-Y) 11 LP addition output stages buffers (R-Y) LINE MEMORY pre-amplifiers SAMPLEAND-HOLD
16
SIGNAL CLAMPING
colour-difference input signals
colour-difference output signals
(B-Y) LINE MEMORY SAMPLEAND-HOLD LP
14
SIGNAL CLAMPING
12
3
3 MHz shifting clock DIVIDEBY-192
(B-Y)
VP1 FREQUENCY PHASE DETECTOR LP digital supply 1 VP2 6 MHz CCO
9
analog supply
TDA4662
sandcastle input
5
SANDCASTLE DETECTOR
2 6 13 15
n.c. n.c. n.c. n.c. DIVIDEBY-2 3 GND2
MED743
7 4, 8
i.c.
10
GND1
Product specification
TDA4662
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Baseband delay line
PINNING SYMBOL VP2 n.c. GND2 i.c. SAND n.c. i.c. i.c. VP1 GND1 Vo(R-Y) Vo(B-Y) n.c. Vi(B-Y) n.c. Vi(R-Y) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION supply voltage for digital part (+5 V) not connected ground for digital part (0 V) internally connected sandcastle pulse input not connected internally connected internally connected supply voltage for analog part (+5 V) ground for analog part (0 V) (R-Y) output signal (B-Y) output signal not connected (B-Y) input signal not connected (R-Y) input signal Fig.2 Pin configuration.
handbook, halfpage
TDA4662
VP2 1 n.c. 2 GND2 3 i.c. 4
16 Vi(R-Y) 15 n.c. 14 Vi(B-Y) 13 n.c.
TDA4662
SAND 5 n.c. 6 i.c. 7 i.c. 8
MED744
12 Vo(B-Y) 11 Vo(R-Y) 10 GND1 9 VP1
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together. SYMBOL VP1 VP2 V5 Vn Tstg Tamb VESD Note 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a SOT38-4 SOT109-1 PARAMETER thermal resistance from junction to ambient in free air 75 220 K/W K/W VALUE UNIT PARAMETER supply voltage (pin 9) supply voltage (pin 1) input voltage on pin 5 voltage on pins 11, 12, 14 and 16 storage temperature operating ambient temperature electrostatic handling for all pins note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -25 0 - MAX. +7 +7 VP + 1.0 VP +150 70 500 V V V V C C V UNIT
1996 Nov 14
4
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
CHARACTERISTICS VP = 5 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz; Tamb = 25 C; measurements taken in Fig.3; unless otherwise specified. SYMBOL VP1 VP2 IP1 IP2 Vi(p-p) PARAMETER analog supply voltage (pin 9) digital supply voltage (pin 1) analog supply current (pin 9) digital supply current (pin 1) input signal (peak-to-peak value) (R-Y) PAL and NTSC (pin 16) (B-Y) PAL and NTSC (pin 14) Vi(max; p-p) maximum symmetrical input signal (peak-to-peak value) (R-Y) for PAL and NTSC (B-Y) for PAL and NTSC R14,16 C14,16 V14,16 Vo(p-p) input resistance during clamping input capacitance input clamping voltage proportional to VP before clipping before clipping 660 840 - - 1.3 - - - - 1.5 - - 40 10 1.7 mV mV k pF V - - 525 665 - - mV mV CONDITIONS MIN. 4.5 4.5 - - 5 5 4.8 0.7 TYP. 6 6 6.0 1.0 MAX. UNIT V V mA mA
Colour-difference input signals
Colour-difference output signals output signal (peak-to-peak value) (R-Y) on pin 11 (B-Y) on pin 12 V11/V12 V11,12 R11,12 Gv VN(rms) V11,12(p-p) ratio of output amplitudes at equal input signals DC output voltage output resistance gain for PAL and NTSC noise voltage (RMS value; pins 11 and 12) unwanted signals (line-locked) (peak-to-peak value) meander spikes S/N(W) td weighted signal-to-noise ratio (pins 11 and 12) time difference between undelayed and delayed output signals (pins 11 and 12) delay of undelayed signals Vo = 1 V (p-p); note 1 ratio Vo/Vi Vi14,16 = 0 V; note 1 Vi14,16 = 0 V; active video; RS = 300 - - - 63.94 40 - - 54 64 60 5 10 - 64.06 80 mV mV dB s ns Vi14,16 = 665 mV (p-p) proportional to VP - - -0.4 2.5 - 5.3 - 1.05 1.33 0 2.9 330 5.8 - - - +0.4 3.3 400 6.3 1.2 V V dB V dB mV
1996 Nov 14
5
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Sandcastle pulse input (pin 5) fBK V5 Vslice I5 C5 Notes 1. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 . 2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing. APPLICATION INFORMATION burst-key frequency/sandcastle frequency top pulse voltage internal slicing level input current input capacitance note 2 14.2 4.0 - - 15.625 - - - 17.0 kHz VP + 1.0 V V5 - 0.5 V 10 10 A pF
V5 - 1.0 -
handbook, full pagewidth
TDA4662
(R-Y) comb filtering colour difference input signals Vi(R-Y) 1 nF 1 nF Vi(B-Y) 14 16 LINE DELAY 11 Vo(R-Y) Vo(B-Y) colour difference output signals
LINE DELAY (B-Y) comb filtering
12 4 8 7
i.c. n.c. n.c. n.c. n.c.
VCO sandcastle input (+5 V) 5 LINE-LOCKED PLL / PULSE PROCESSING +5.1 V 9 +5.1 V 1
(1)
2 6 13 15
10
(1)
3
100 nF 10 10 22 F
100 nF 560 5.1 V
MED745
+12 V
(1) Positioned close to pins.
Fig.3 Application circuit.
1996 Nov 14
6
Philips Semiconductors
Product specification
Baseband delay line
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil)
TDA4662
SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.030
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1996 Nov 14
7
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 0.041 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.0098 0.057 0.0039 0.049
0.019 0.0098 0.39 0.014 0.0075 0.38
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-01-23
1996 Nov 14
8
Philips Semiconductors
Product specification
Baseband delay line
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA4662
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Nov 14
9
Philips Semiconductors
Product specification
Baseband delay line
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4662
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Nov 14
10
Philips Semiconductors
Product specification
Baseband delay line
NOTES
TDA4662
1996 Nov 14
11
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/03/pp12
Date of release: 1996 Nov 14
Document order number:
9397 750 01156

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